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Hardware/Software Codesign (2V, 1U)

Part of Master's Program Computer Science and Computer Engineering

Lecture number: L.079.05802
Term Summer term 2017
Lecturers Prof. Dr. Christian Plessl, Dr. Tobias Kenter
Contact Office: O2.167, Email: christian.plessl@uni-paderborn.de, Tel: 05251-605399

Goals and Contents of the Lecture

Hardware/Software Codesign denotes the integrated and automated design of hardware and software in computer systems, in particular embedded systems. Virtually any state of the art embedded system, e.g. mobile phone, game console, or automotive and industrial control system, comprises cooperating hard and software components. Driven by the demand for new functionalities and the rapid progress in the area of microelectronics these systems become increasingly complex. Hence the use of computer aided design methods is not only necessary to deal with the complexity of these systems, but also to reduce design cost and time.

The goal of this course in Hardware/Software Codesign is to introduce the fundamental problems in the automated design of complex computer systems and to present the most important methods for modeling and solving these problems. More detailed information on the contents and organization of the lecture will be published on this webpage. If you have any questions, feel free to contact Prof. Plessl.

Schedule and Materials

The course will be held weekly on Mondays in room O1.258 from 13:15-14:45 and 15:00-15:45. The exercises will be integrated within the lecture.

The current schedule is presented in the table below, which is constantly updated.

Lectures taught by Christian Plessl are marked with CP, lectures taught by Tobias Kenter are marked with TK.

Lecture schedule Hardware/Software Codesign SS2017
DateContentsLecturerMaterialsExercises
April 24, 2017
  • Introduction, lecture organization
CP
May 1, 2017
  • Public holiday, no lecture
May 8, 2017
  • Target Architectures
CP
May 15, 2017
  • Target Architectures (cntd.)
TK
May 22, 2017
  • Target Architectures (cntd.)
CP
May 29, 2017
  • Introduction to Compilers
CP
June 5, 2017Public holiday, no lecture
June 12, 2017
  • Introduction to the LLVM Compiler Framework
  • Architecture Synthesis
TK
June 19, 2017
  • Architecture Synthesis (cntd.)
TK
June 26, 2017
  • Architecture Synthesis (cntd.)
  • System Partitioning
TK
July 3, 2017
  • System Partitioning (cntd.)
TK
July 10, 2017
  • Discussion Programming Exercise 1
  • System Partitioning (cntd.)
TK
July 17, 2017
  • Design Space Exploration
  • Estimation
CP
July 24, 2017
  • Case Study
  • Closing Session
CP

Exercises

The exercise sheets can be downloaded from the website. However, instead of discussing the exercises in a separate exercise event, I will integrate them into the regular lecture. The solutions of the exercises will be discussed in class, there will be no reference solutions in written form available.

Exam

Depending on your situation (study program) there are two kinds of exams in HW/SW Codesign: 1) Examination as an Individual exam (Einzelprüfung) or 2) examination as a Module exam. Please schedule your exam as early as possible by sending an email to my secretary Mrs. Michaela Kemper.

Literature

This lecture has been designed to be widely self-contained. Hence you should be able to follow the lecture by studying the lecture notes (slides) only. If you would to dive deeper into a particular topic, you may refer to the following literature on which the lecture is based. 

Books

  • P. Schaumont. A Practical Introduction to Hardware/Software Codesign. Springer, 2010. doi:10.1007/978-1-4419-6000-9
  • J. Teich and C. Haubelt. Digitale Hardware/Software-Systeme. Synthese und Optimierung. Springer, Berlin Heidelberg New York, 2nd edition, 2007. doi:10.1007/978-3-642-05356-6_1
  • G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994. 

Articles

  • B. W. Kernighan, and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell Systems Technical Journal, 49:291–307, 1970.
  • T. Kenter, M. Platzner, C. Plessl, and M. Kauschke. Performance estimation framework for automated exploration of CPU-accelerator architectures. In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), pages 177–180, New York, NY, USA, Feb. 2011. doi:10.1145/1950413.1950448
Contact

Prof. Dr. Christian Plessl

High-Performance IT Systems

Christian Plessl
Phone:
+49 5251 60-5399
Fax:
+49 5251 60-1714
Office:
O2.167
Web:

Dr. Tobias Kenter

High-Performance IT Systems

Phone:
+49 5251 60-4340
Fax:
+49 5251 60-1714
Office:
O2.161

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